Non-generic floating-point software support for embedded media processing

International audienceThis paper presents some work in progress on the design and implementation of efficient floating-point software support for embedded integer processors. We provide quantitative evidence of the benefits of supporting various non-generic (that is, specialized, fused, or simultaneous) operations in addition to the five basic arithmetic operations: for individual calls, speedups range from 1.12 to 4.86, while on DSP kernels and benchmarks, our approach allows us to be up to 1.34x faster

How to square floats accurately and efficiently on the ST231 integer processor

We consider the problem of computing IEEE floating-point squares by means of integer arithmetic. We show how the specific properties of squaring can be exploited in order to design and implement algorithms that have much lower latency than those for general multiplication, while still guaranteeing correct rounding. Our algorithm descriptions are parameterized by the floating-point format, aim at high instruction-level parallelism (ILP) exposure, and cover all rounding modes. We show further that their C implementation for the binary32 format yields efficient codes for targets like the ST231 VLIW integer processor from STMicroelectronics, with a latency at least 1.75x smaller than that of general multiplication in the same context

A new binary floating-point division algorithm and its software implementation on the ST231 processor

This paper deals with the design and implementation of low latency software for binary floating-point division with correct rounding to nearest. The approach we present here targets a VLIW integer processor of the ST200 family, and is based on fast and accurate programs for evaluating some particular bivariate polynomials. We start by giving approximation and evaluation error conditions that are sufficient to ensure correct rounding. Then we describe the heuristics used to generate such evaluation programs, as well as those used to automatically validate their accuracy. Finally, we propose, for the binary32 format, a complete C implementation of the resulting division algorithm. With the ST200 compiler and compared to previous implementations, the speed-up observed with our approach is by a factor of almost 1.8

Étude formelle de l'implémentation du code des impôts

National audienceThe tax code, as a legislative text, defines a mathematical function that computes the income tax of a fiscal household. In order to collect taxes, this function is implemented as an algorithm by the Direction Générale des Finances Publiques (DGFiP), using a domain specific language called M (standing for "Macro-language"). We propose a formal semantics of the M language, tested thanks to data published by the DGFiP. This formalization, coupled with the public release by the DGFiP of the codebase used to compute the income tax, allowed us to produce a fully formalized artifact encoding the fragment of the tax code describing the income tax computation. We demonstrate the usefulness of such a formalization thanks to a prototype that uses an SMT solver to infer meta-properties on the income tax computation. These meta-properties could complete and refine the existing economical analysis of the redistributive effects of the income tax, as well as various social benefits. More generally, a systematic formalization of the algorithmic fragments of the law would raise the assurance level on the coherence of the French socio-fiscal system. This work has led to the development of three software artifacts: a mechanized semantics for M, an interpreter and compiler for M based on this semantics (written in OCaml), and a Python prototype of encoding the income tax computation into the Z3 SMT solver.Le code des impôts définit dans son texte législatif une fonction mathématique per-mettant de calculer l'impôt sur le revenu d'un foyer fiscal. Afin de recouvrer l'impôt, cette fonction est implémentée sous la forme d'un algorithme par la Direction Générale des Finances Publiques (DGFiP), en utilisant un langage dédié appelé M (pour macro-langage). Nous proposons une sémantique formelle du langage M, testée grâce aux données publiées par la DGFiP. Cette formalisation, couplée à la publication par la DGFiP de la base de code M calculant l'impôt, nous donne accès à une formalisation complète de la portion du code des impôts définissant l'algorithme de calcul de l'impôt sur le revenu. Nous démontrons l'utilité d'une telle formalisation grâce à un prototype à base de solveurs SMT permet-tant d'inférer des méta-propriétés sur le calcul de l'impôt. Ces méta-propriétés peuvent ensuite compléter et affiner les analyses économiques existantes sur les effets redistributifs de l'impôt sur le revenu, mais aussi de diverses allocations. Plus généralement, une for-malisation systématique des portions algorithmiques de la loi permettrait d'augmenter le niveau d'assurance sur la cohérence du système socio-fiscal français. Trois artefacts logiciels accompagnent cet article : une formalisation mécanisée de la sémantique du langage M, un compilateur pour le langage M basé sur cette sémantique, ainsi que le prototype d'encodage du code des impôts dans le solveur SMT Z3

ASIC for High-Speed-Gating and Free Running Operation of SPADs

Single photon detection at telecom wavelengths is of importance in many industrial applications ranging from quantum cryptography, quantum optics, optical time domain reflectometry, non-invasive testing of VLSI circuits, eye-safe LIDAR to laser ranging. In practical applications, the combination of an InGaAs/InP APD with an appropriate electronic circuit still stands as the best solution in comparison with emerging technologies such as superconducting single photon detectors, MCP-PMTs for the near IR or up-conversion technique. An ASIC dedicated to the operation of InGaAs/InP APDs in both gated mode and free-running mode is presented. The 1.6mm2 chip is fabricated in a CMOS technology. It combines a gate generator, a voltage limiter, a fast comparator, a precise timing circuit for the gate signal processing and an output stage. A pulse amplitude of up to +7V can be achieved, which allows the operation of commercially available APDs at a single photon detection probability larger than 25% at 1.55μm. The avalanche quenching process is extremely fast, thus reducing the afterpulsing effects. The packaging of the diode in close proximity with the quenching circuit enables high speed gating at frequencies larger than 10MHz. The reduced connection lengths combined with impedance adaptation technique provide excellent gate quality, free of oscillations or bumps. The excess bias voltage is thus constant over the gate width leading to a stable single photon detection probability and timing resolution. The CMOS integration guarantees long-term stability, reliability and compactness

Étude formelle de l'implémentation du code des impôts

The tax code, as a legislative text, defines a mathematical function that computes the income tax of a fiscal household. In order to collect taxes, this function is implemented as an algorithm by the Direction Générale des Finances Publiques (DGFiP), using a domain specific language called M (standing for "Macro-language"). We propose a formal semantics of the M language, tested thanks to data published by the DGFiP. This formalization, coupled with the public release by the DGFiP of the codebase used to compute the income tax, allowed us to produce a fully formalized artifact encoding the fragment of the tax code describing the income tax computation. We demonstrate the usefulness of such a formalization thanks to a prototype that uses an SMT solver to infer meta-properties on the income tax computation. These meta-properties could complete and refine the existing economical analysis of the redistributive effects of the income tax, as well as various social benefits. More generally, a systematic formalization of the algorithmic fragments of the law would raise the assurance level on the coherence of the French socio-fiscal system. This work has led to the development of three software artifacts: a mechanized semantics for M, an interpreter and compiler for M based on this semantics (written in OCaml), and a Python prototype of encoding the income tax computation into the Z3 SMT solver.Le code des impôts définit dans son texte législatif une fonction mathématique per-mettant de calculer l'impôt sur le revenu d'un foyer fiscal. Afin de recouvrer l'impôt, cette fonction est implémentée sous la forme d'un algorithme par la Direction Générale des Finances Publiques (DGFiP), en utilisant un langage dédié appelé M (pour macro-langage). Nous proposons une sémantique formelle du langage M, testée grâce aux données publiées par la DGFiP. Cette formalisation, couplée à la publication par la DGFiP de la base de code M calculant l'impôt, nous donne accès à une formalisation complète de la portion du code des impôts définissant l'algorithme de calcul de l'impôt sur le revenu. Nous démontrons l'utilité d'une telle formalisation grâce à un prototype à base de solveurs SMT permet-tant d'inférer des méta-propriétés sur le calcul de l'impôt. Ces méta-propriétés peuvent ensuite compléter et affiner les analyses économiques existantes sur les effets redistributifs de l'impôt sur le revenu, mais aussi de diverses allocations. Plus généralement, une for-malisation systématique des portions algorithmiques de la loi permettrait d'augmenter le niveau d'assurance sur la cohérence du système socio-fiscal français. Trois artefacts logiciels accompagnent cet article : une formalisation mécanisée de la sémantique du langage M, un compilateur pour le langage M basé sur cette sémantique, ainsi que le prototype d'encodage du code des impôts dans le solveur SMT Z3

More accurate complex multiplication for embedded processors

International audienceThis paper presents some work in progress on the development of fast and accurate support for complex floating-point arithmetic on embedded processors. Focusing on the case of multiplication, we describe algorithms and implementations for computing both the real and imaginary parts with high relative accuracy. We show that, in practice, such accuracy guarantees can be achieved with reasonable overhead compared with conventional algorithms (which are those offered by current implementations and for which the real or imaginary part of a product can have no correct digit at all). For example, the average execution-time overheads when computing an FFT on the ARM Cortex-A53 and -A57 processors range from 1.04x to 1.17x only, while arithmetic costs suggest overheads from 1.5x to 1.8x